Timed SystemC waiting-state automata - ENSTA Paris - École nationale supérieure de techniques avancées Paris Accéder directement au contenu
Communication Dans Un Congrès Année : 2009

Timed SystemC waiting-state automata

Résumé

System-Level Modeling using system-level languages like SystemC or SystemVerilog is gaining more and more popularity. They are supposed to provide the garantee of critical functional properties about the interaction between concurrent processes like determinism or liveness up to a basic unit, the delta-cycle. Additionnally to this functional correctness, system level models should also provide valuable information about important non-functional properties like time constraints. Since timing properties (execution times, delays, periods, etc.) are especially important in performance verification of multiprocessing real-time embedded systems, we propose a formal model based on SystemC waiting-state automata that conforms to the SystemC scheduler up to delta-cycles and that also conforms to the provided time constraints.
Fichier non déposé

Dates et versions

hal-00672908 , version 1 (22-02-2012)

Identifiants

  • HAL Id : hal-00672908 , version 1

Citer

Nesrine Harrath, Bruno Monsuez. Timed SystemC waiting-state automata. Third International Workshop on Verification and Evaluation of Computer and Communication Systems, Jul 2009, Rabat, Morocco. ⟨hal-00672908⟩

Collections

ENSTA ENSTA_U2IS
31 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More